14.5 When a forward bias is applied to a p-n junction, it

(a) raises the potential barrier.

(b) reduces the majority carrier current to zero.

(c) lowers the potential barrier.

(d) None of the above.

The current flow through the resistance in the given circuit is : (Cut-off voltage for both diodes is 0.7 V)

A n-p-n transistor can be used as

The output (X) of the logic circuit shown in figure will be

 

In the above diagram, balance length for E' is ℓ₀. If cross sectional area of wire AB is doubled then what will be new balancing length ?

The figure shows a logic circuit with two inputs A and B and an output C. The voltage wave forms of A, B and C are as given, then logic circuit will be equivalent to :-