14.13 You are given two circuits as shown in Fig. 14.38, which consist of NAND gates. Identify the logic operation carried out by the two circuits.

14.13 The output of the left NAND gate will be $\stackrel{?}{A.B}$ , as shown in the following figure:

Hence, the output of the combination of two NAND gates is given as:

Y = ( $\stackrel{?}{A.B}$ ).( $\stackrel{?}{A.B}$ ) = $\stackrel{?}{A.B}$ + $\stackrel{?}{A.B}$  = AB

Hence the circuit functions as an AND gate.

$\stackrel{?}{A}$ is the output of the upper left of the NAND gate and $\stackrel{?}{B}$  is the output of the lower half of the NAND gate, as shown in the following figure.

Hence, the output of the combination of the NAND gates will be given as:

Y = $\stackrel{?}{A}$ . $\stackrel{?}{B}$  = $\stackrel{?}{A}$ + $\stackrel{?}{B}$  = A + B

Hence, this circuit functions as an OR gate.

<p><strong>14.13 </strong>The output of the left NAND gate will be <span contenteditable="false"> <math> <mover accent="true"> <mrow> <mrow> <mi>A</mi> <mo>.</mo> <mi>B</mi> </mrow> </mrow> <mo>?</mo> </mover> </math> </span> , as shown in the following figure:</p><div><div><picture><source srcset="https://images.shiksha.com/mediadata/images/articles/1728033899phpjCFMIj_480x360.jpeg" media="(max-width: 500px)"><img src="https://images.shiksha.com/mediadata/images/articles/1728033899phpjCFMIj.jpeg" alt="" width="229" height="64"></picture></div><div><p>Hence, the output of the combination of two NAND gates is given as:</p><p>Y = ( <span contenteditable="false"> <math> <mover accent="true"> <mrow> <mrow> <mi>A</mi> <mo>.</mo> <mi>B</mi> </mrow> </mrow> <mo>?</mo> </mover> </math> </span>).(<span contenteditable="false"> <math> <mover accent="true"> <mrow> <mrow> <mi>A</mi> <mo>.</mo> <mi>B</mi> </mrow> </mrow> <mo>?</mo> </mover> </math> </span> ) = <span contenteditable="false"> <math> <mover accent="true"> <mrow> <mrow> <mi>A</mi> <mo>.</mo> <mi>B</mi> </mrow> </mrow> <mo>?</mo> </mover> </math> </span>+<span contenteditable="false"> <math> <mover accent="true"> <mrow> <mrow> <mi>A</mi> <mo>.</mo> <mi>B</mi> </mrow> </mrow> <mo>?</mo> </mover> </math> </span> &nbsp;= AB</p><p>Hence the circuit functions as an AND gate.</p><p><span contenteditable="false"> <math> <mover accent="true"> <mrow> <mrow> <mi>A</mi> </mrow> </mrow> <mo>?</mo> </mover> </math> </span>is the output of the upper left of the NAND gate and <span contenteditable="false"> <math> <mover accent="true"> <mrow> <mrow> <mi>B</mi> </mrow> </mrow> <mo>?</mo> </mover> </math> </span>&nbsp;is the output of the lower half of the NAND gate, as shown in the following figure.</p><div><div><picture><source srcset="https://images.shiksha.com/mediadata/images/articles/1728034026phpJDU4rE_480x360.jpeg" media="(max-width: 500px)"><img src="https://images.shiksha.com/mediadata/images/articles/1728034026phpJDU4rE.jpeg" alt="" width="227" height="100"></picture></div></div><p>Hence, the output of the combination of the NAND gates will be given as:</p><p>Y = <span contenteditable="false"> <math> <mover accent="true"> <mrow> <mrow> <mi>A</mi> </mrow> </mrow> <mo>?</mo> </mover> </math> </span>.<span contenteditable="false"> <math> <mover accent="true"> <mrow> <mrow> <mi>B</mi> </mrow> </mrow> <mo>?</mo> </mover> </math> </span> &nbsp;= <span contenteditable="false"> <math> <mover accent="true"> <mrow> <mrow> <mi>A</mi> </mrow> </mrow> <mo>?</mo> </mover> </math> </span>+<span contenteditable="false"> <math> <mover accent="true"> <mrow> <mrow> <mi>B</mi> </mrow> </mrow> <mo>?</mo> </mover> </math> </span> &nbsp;= A + B</p><p>Hence, this circuit functions as an OR gate.</p></div></div>

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